PS2 Linux .... on PCSX2
#1
Anyone knows if it possible and how to use Linux on the PSXC2?
Just talking with my friend here and playing around with the idea of making a VirtualBox of W7 running PSX2 running Linux running Dosbox because ... fun.
CPU : Intel i7-2600K
GPU : nVidia Geforce GTX 970
OS : Windows 8.1 x64
RAM : 16GB Corsair Vengance DDR3
PCSX2 : Constantly changing.
Reply

Sponsored links

#2
is there a working usb plugin that supports keyboard? Without a keyboard it might be complicated.
Reply
#3
In addition to the keyboard issue, the bigger problem is probably going to be HDD support.

[Image: gsdx_20150303141221c3u10.png]
It loads up fine initially, at least.
I fiddled with it a couple years back on my PS2, even got stuff like mplayer to run, but I can't remember anything about the install procedure, and my Japanese knowledge is non-existent, so I don't know where it fails here exactly, since I can't get very far. Not far enough to have an actual console with English output to have an idea what's going on, at any rate.

This would definitely be interesting, but my guess is the mentioned issues (keyboard, HDD) are roadblocks that can't be easily overcome with the current state of PCSX2.

Edit: Turns out, keyboard is not an issue, thanks to this plugin by Ge-Force. Simply works.

That said, that doesn't help for now. If someone with Japanese knowledge wants to take a look at these 2 messages, that would be nice.
With disc 1 active
With disc 2 active

Edit 2: Reading a bit more into this, I think there were English language releases of the install discs, as well? I'm not too sure, and it's probably going to be hard to find one, at any rate. Might have to keep an eye on ebay. Plus it seems like there are various incompatibility issues between different hardware revisions, not sure how that would affect it running on PCSX2.
Reply
#4
[Image: gsdx_20150303160546suogs.png]

Got a bit further. Also, there is apparently a dev9 plugin that provides HDD support (available in the download section of the site), and while it works in that it creates the image, PS2 Linux will hang after loading the kernel if it's enabled (it appears to be stuck in some kind of infinite loop of reading 2 different adresses). If enabling HDD support in the gigaherz' dev9 plugin (via registry) and pointing it to the image created by megadev9, it will eventually go back to the boot environment with a different Japanese message and no obvious way to continue.
So that's a problem. But now I'm curious how far you can actually get, so I might spend some more time with this. Smile

Edit: So, removing USB keyboard and HDD for now, that still leaves us with a system that hangs at that point.
Code:
EE: Unrecognized op 177
EE: Unrecognized op 1875
branch 1000e000 in delay slot!

Running the EE in interpreter mode leaves us with:
Code:
COP0_TLBWR 0:0,7fffe105,0,7311c
Repeated ad infitum.

That's the point where I'm out and someone with more inside knowledge of PCSX2 has to step in. Wink

Edit 2: One more observation, accessing and formatting the megadev9 HDD with ulaunchelf and creating all the standard PS2 system partitions (__net, __boot etc.) works fine, but has no effect on PS2 Linux itself hanging with the HDD enabled.

Edit 3: One more sidenote, I find it interesting that ulaunchelf doesn't boot with the EE in interpreter mode. Switching to recompiler and back to interpreter fixes it, but I wouldn't have expected to run into issues with the interpreter that aren't there with the EE recompiler.
Reply
#5
Interesting how this thread developed.

(03-03-2015, 05:12 PM)Eloris Wrote:
Code:
COP0_TLBWR 0:0,7fffe105,0,7311c

(03-03-2015, 05:12 PM)Eloris Wrote:
Code:
TLBWR

(03-03-2015, 05:12 PM)Eloris Wrote:
Code:
TLB
I think we need a TLB genius to understand this message... gregory where are you?

Also maybe interesting why interpreter isn't working...
Reply
#6
TLB miss won't be supported on the recompiler only interpreter support them.

TLBWR => write TLB entry into a random position. The random position is somewhere between (reserved OS entries; Max TLB entries). Normally the counter must be incremened every instruction. (or maybe every TLB write). PCSX2 just keeps it to 0. By the way I'm not sure we support the ASID too.

Quote:COP0_TLBWR 0:0,7fffe105,0,7311c
Is it always the same line?

It details, set entry 0 with a 4K page with ASID 0x5 (that strange value is not valid, it ought to be 0x7fffe005). On
Virtual address 0x7FFFE000 => null address invalid
Virtual address 0x7FFFF000 => physical address 0x1CC4000 (likely IOP stuff backdoor access, potentially not emulated). Strangely the page is marked as invalid. (Marked dirty and cacheable)

Edit: for the details of the fields, get tx79architecture doc on google chapter 4.2
Reply
#7
(03-03-2015, 11:52 PM)gregory Wrote: Is it always the same line?
Yes.

It's repeated very rapidly, as well, letting it run for about 5 seconds at that spot generates about 50.000 messages. If that matters at all.
Reply
#8
Hum time to contribute Tongue2 I think it would be a good idea to implement the random register behavior (and potentially the wired register).

From the spec
Quote:The Random register is a read-only register. The least significant six bits index an entry
in the TLB. This register decrements every cycle an instruction is executed. Its value
ranges between an upper and a lower bound, as follows:


A lower bound is set by the number of TLB entries reserved for exclusive use by
the operating system (the contents of the Wired register).
An upper bound is set by the total number of TLB entries (47 maximum).
The Random register specifies the entry in the TLB that is affected by the TLB Write
Random (TLBWR) instruction. The register does not need to be read for this purpose;
however, the register is readable to verify proper operation of the processor.
To simplify testing, the Random register is set to the value of the upper bound upon
system reset. This register is also set to the upper bound when the Wired register is
written.

By the way, is it the first TLB write entry?
Reply
#9
(03-04-2015, 12:07 AM)gregory Wrote: By the way, is it the first TLB write entry?

It is. Smile
Reply
#10
Run with a debug build. It could yield more info.
Reply




Users browsing this thread: 1 Guest(s)