01-16-2022, 06:12 PM
Inspect these codes:
https://forums.pcsx2.net/Thread-60-fps-c...#pid624122
The 0x0028F4C4 (PAL) offset is handling the frame limiter. The 0x0028F500 offset contains the address of the display buffer. As you can see they are next to each other.
In the first screenshot you posted the game is writing 0x66 (a0 register) into the 0x12000000. The value 0x66 is loaded into the a0 register from the EE memory address specified in the s0 register (0x00351488). So the frame limiter switch may be (not has to be) somewhere around that offset.
https://forums.pcsx2.net/Thread-60-fps-c...#pid624122
The 0x0028F4C4 (PAL) offset is handling the frame limiter. The 0x0028F500 offset contains the address of the display buffer. As you can see they are next to each other.
In the first screenshot you posted the game is writing 0x66 (a0 register) into the 0x12000000. The value 0x66 is loaded into the a0 register from the EE memory address specified in the s0 register (0x00351488). So the frame limiter switch may be (not has to be) somewhere around that offset.